To optimize power consumption, a processor system can be power gated or clock gated when idled for a period of time. In some situations, power gating or clock gating may be managed through software control. As such, power management may be achieved by explicitly entering low power states through software control. For instance, power gating may be achieved by gating power field effect transistors (FETs) to an off condition, wherein the power FETs control distribution of power to the processor system. In addition, power saving may be achieved by gating a clock signal that is distributed throughout the processor system. Without an active clock signal, the processor system will idles and consume a minimum amount of power.
The processor system may be placed into various degrees of low power states. The selection of the depth of the low power state selected depends on how quickly the processor system is required to be activated from that state. That is, when the processor system needs to wake up, such as due to some wake event like a periodic timer interrupt, then powering on and restoring context adds to the latency of a wake up process. The deeper the lower power state, the more time is required in waking up the processor system. As such, if the processor system is able to tolerate a longer wake up period, then the processor system may be placed into a deeper low power state. On the other hand, if the processor is only able to tolerate a short wake up period, then the processor system may be placed into a shallower low power state.
Additionally, in some situations the user experience will affect how deep of a lower power state to put the processor system. It may be determined that the user experience is poor when there is too long of a wake up latency period coming out of a low power state. In that case, power savings is sacrificed as the processor system may be placed into a shallower low power state to achieve lower wake up latencies for purposes of giving a better user experience.
However, in order to satisfy the various constraints, the processor system is placed in more shallow low power states. This undermines the goal of achieving the lowest possible low power state so that the most power is saved in the least amount of time.
It is desirous to put the processor system in the deepest lower power state possible for the longest possible amount of time. This allows for the most power saving to be achieved.